1 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. gnd/soe q 0 q 1 ref fs pll fb v ddq /pe q 2 q 3 q 4 q 5 q 6 q 7 february 2000 1999 integrated device technology, inc. dsc-5813/- c idtcsp59920 commercial/industrial temperature ranges low skew pll clock driver turboclock? jr. description: the csp59920 is a high fanout phase lock loop clock driver in- tended for high performance computing and data-communications ap- plications. the csp59920 has cmos outputs. the csp59920 maintains cypress cy7b9920 compatibility while providing two additional features: synchronous output enable (gnd/ soe ), and positive/negative edge synchronization (v ddq /pe). when the gnd/ soe pin is held low, all outputs are synchronously enabled (cy7b9920 compatibility). however, if gnd/ soe is held high, all out- puts except q2 and q3 are synchronously disabled. furthermore, when the v ddq /pe is held high, all outputs are syn- chronized with the positive edge of the ref clock input (cy7b9920 compatibility). when v ddq /pe is held low, all outputs are synchronized with the negative edge of ref. the fb signal is compared with the input ref signal at the phase detector in order to drive the vco. phase differences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. features: ? eight zero delay outputs ? selectable positive or negative edge synchronization ? synchronous output enable ? output frequency: 25mhz to 85mhz ? cmos outputs ? 3 skew grades: csp59920-2: t skew0 <250ps csp59920-5: t skew0 <500ps csp59920-7: t skew0 <750ps ? 3-level input for pll range control ? pll bypass for dc testing ? external feedback, internal loop filter ? 46ma i ol high drive outputs ? low jitter: <200ps peak-to-peak ? outputs drive 50 w terminated lines ? pin compatible with cypress cy7b9920 ? available in soic package functional block diagram
2 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ref fs nc v ddq /pe q 0 q 1 gnd q 2 q 3 gnd test nc gnd/soe q 7 q 6 gnd q 5 q 4 fb v ddn v ddn v ddq v ddn v ddn so24-2 soic top view absolute maximum ratings (1) symbol rating max. unit supply voltage to ground C0.5 to +7 v v i dc input voltage C0.5 to +7 v maximum power dissipation (t a = 85c) 530 mw t stg storage temperature range C65c to +150c c note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (t a = 25 c, f = 1mhz, v in = 0v) parameter description typ. max. unit c in input capacitance 5 7 pf note: 1. capacitance applies to all inputs except test and fs. it is characterized but not production tested. pin description pin name type description ref in reference clock input fb in feedback input test (1) in when mid or high, disables pll (except for conditions of note 1). ref goes to all outputs. set low for normal operation. gnd/ soe (1) in synchronous output enable. when high, it stops clock outputs (except q 2 and q 3 ) in a low state - q 2 and q 3 may be used as the feedback signal to maintain phase lock. set gnd/ soe low for normal operation. v ddq /pe in selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge of the reference clock. fs (2) in frequency range select. 3 level input. fs = gnd: 25 to 35mhz. fs = mid (or open): 35 to 60mhz fs = v dd : 60 to 85mhz q 0 - q 7 out 8 clock output v ddn pwr power supply for output buffers v ddq pwr power supply for phase locked loop and other internal circuitry gnd pwr ground notes: 1. when test = mid and gnd/ soe = high, pll remains active. 2. this input is wired to v dd , gnd, or unconnected. default is mid level. if it is switched in the real time mode, the outputs may glitch, and the pll may require an additional lock time before all data sheet limits are achieved.
3 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. recommended operating range csp59920-5, -7 (industrial) csp59920-2 (commercial) symbol description min. max. min. max. unit v dd power supply voltage 4.5 5.5 4.75 5.25 v t a ambient operating temperature -40 +85 0 +70 c dc electrical characteristics over operating range symbol parameter conditions min. max. unit v ih input high voltage guaranteed logic high (ref, fb inputs only) v dd - 1.35 v v il input low voltage guaranteed logic low (ref, fb inputs only) 1.35 v v ihh input high voltage (1) 3-level inputs only v dd - 1 v v imm input mid voltage (1) 3-level inputs only v dd /2 - 0.5 v dd /2+0.5 v v ill input low voltage (1) 3-level inputs only 1 v i in input leakage current (ref, fb inputs only) v in = v dd or gnd v dd = max. 5a v in = v dd high level 200 i 3 3-level input dc current (test, fs) v in = v dd /2 mid level 50 a v in = gnd low level 200 i pu input pull-up current (v ddq /pe) v dd = max., v in = gnd 100 a i pd input pull-down current (gnd/ soe )v dd = max., v in = v dd 100 a v oh output high voltage v dd = min., i oh = - 16ma v v dd = min., i oh = - 40ma v dd - 0.75 v v ol output low voltage v dd = min., i ol = 46ma 0.45 v i os output short circuit current (2) v dd = max., v o = gnd n/a ma notes: 1. these inputs are normally wired to v dd , gnd, or unconnected. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched, the function and timing of the outputs may be glitched, and the pll may require an additional t lock time before all datasheet limits are achieved. 2. csp59920 outputs are not to be shorted. power supply characteristics symbol parameter test conditions typ. max. unit i ddq quiescent power supply current v dd = max., test = mid, ref = low, gnd/ soe = low, all outputs unloaded 10 40 ma d i dd power supply current per input high v dd = max., v in = 3.4v 0.4 1.5 ma i ddd dynamic power supply current per output v dd = max., c l = 0pf 100 160 m a/mhz i tot total power supply current v dd = 5v, f ref = 25mhz, c l = 240pf (1) 53 ma v dd = 5v, f ref = 33mhz, c l = 240pf (1) 63 ma v dd = 5v, f ref = 66mhz, c l = 240pf (1) 117 ma note: 1. for eight outputs, each loaded with 30pf.
4 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. notes: 1. all timing tolerances apply for f nom 3 25mhz. guaranteed by design and characterization, not subject to production testing. 2. skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. t skew is the skew between all outputs. see ac test loads. 4. t dev is the output-to-output skew between any two devices operating under the same conditions (v dd , ambient temperature, air flow, etc.) 5. t lock is the time that is required before synchronization is achieved. this specification is valid only after v dd is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits. 6. t pd is measured with ref input rise and fall times (from 0.8v to 2.0v) of 1.0ns. 7. refer to input timing requirements for more detail. input timing requirements symbol description (1) min. max. unit t r , t f maximum input rise and fall times, 0.8v to 2v 10 ns/v t pwc input clock pulse, high or low 3 ns d h input duty cycle 10 90 % r ef reference clock input 25 85 mhz note: 1. where pulse width implied by d h is less than t pwc limit, t pwc limit applies. switching characteristics over operating range csp59920-2 csp59920-5 csp59920-7 symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f ref ref frequency range fs = low 25 35 25 35 25 35 mhz fs = mid 35 60 35 60 35 60 fs = high 60 85 60 85 60 85 t rpwh ref pulse width high (1, 7) 3 3 3 ns t rpwl ref pulse width low (1, 7) 3 3 3 ns t skew zero output skew (all outputs) (1, 3) 0.1 0.25 0.25 0.5 0.3 0.75 ns t dev device-to-device skew ( 1,2, 4) 0.75 1.25 1.65 ns t pd ref input to fb propagation delay ( 1,6) - 0.25 00.25 - 0.5 00.5 - 0.7 00.7ns t odcv output duty cycle variation from 50% (1) - 1.2 01.2 - 1.2 01.2 - 1.5 01.5ns t orise output rise time (1) 0.5 2 2.5 0.5 2 3.5 0.5 3 5 ns t ofall output fall time (1) 0.5 2 2.5 0.5 2 3.5 0.5 3 5 ns t lock pll lock time (1) 0.5 0.5 0.5 ms t jr cycle-to-cycle output jitter rms 25 25 25 ps peak-to-peak 200 200 200
5 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. 100 w output v dd c l c l = 50pf (c l = 30pf for -2 and -5 devices) t orise t ofall 0.8 v dd 0.2 v dd 3ns 3ns 80% 20% 0v vth = 0.5v dd v dd 100 w ac test loads and waveforms test load cmos input test waveform cmos output waveform ref fb q other q t ref t pd t skew t skew t jr t odcv t odcv t rpw h t rpwl ac timing diagram notes: skew: the time between the earliest and the latest output transition among all outputs when all are loaded with 50pf (30pf for -2 and -5) and terminated with v dd /2. t skew : the skew between all outputs. t dev : the output-to-output skew between any two devices operating under the same conditions (v dd , ambient temperature, air flow, etc.) t odcv : the deviation of the output from a 50% duty cycle. t orise and t ofall are measured between 0.2v dd and 0.8v dd . t lock : the time that is required before synchronization is achieved. this specification is valid only after v dd is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
6 commercial and industrial temperature ranges idtcsp59920 low skew pll clock driver turboclock jr. corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. turboclock is a registered trademark of integrated device technology, inc. ordering information idtcsp xxxxx xx x package process device type blank i 59920-2 59920-5 59920-7 low skew pll clock driver turboclock jr. small outline ic (300-mil) (so24-2) so commercial (0c to +70c) industrial (-40c to +85c)
|
